BPU — Processing Unit agent-readable instructions
The BPU is a hardware concept for evaluating policy circuits before an AI action reaches the host. The enforceable path is software today; FPGA and silicon phases remain roadmap work.
- Software policy circuits: Current work compiles policy boundaries into software guard modules.
- FPGA validation: Roadmap work would validate the execution model on hardware.
- Silicon enforcement: Future ASIC work would require separate hardware evidence before public claims expand.
BPU — Processing Unit
Policy enforcement as a hardware roadmap.
The BPU is a hardware concept for evaluating policy circuits before an AI action reaches the host. The enforceable path is software today; FPGA and silicon phases remain roadmap work.
Architecture Overview
Separate the current product from the hardware roadmap.
Today the enforceable surface is software policy circuits. FPGA and silicon phases require their own evidence.
The Non-Maskable Block
A physical gate would change where final policy decisions are enforced, but the public claim must stay phase-specific.
Software policy circuits
Current work compiles policy boundaries into software guard modules.
FPGA validation
Roadmap work would validate the execution model on hardware.
Silicon enforcement
Future ASIC work would require separate hardware evidence before public claims expand.
Roadmap
Software is available now. FPGA validates the execution model next. Silicon turns the same boundary into a physical gate.
Phase 1 is available now.
Policy circuits are the current path. Hardware phases remain evidence-gated roadmap work.